fpga - Verilog Serial to Parallel Conversion -

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i having problem converting serial input external device, parallel input xilinx spartan 3e fpga.
first module turns serial parallel, , second outputs first bit of po (parallel output) led. of right after checking on scope signal coming out of led following serial input , not retaining value of po[0]

module spi_logic (c, si, po, notcs);  input  c,si,notcs;  output reg [15:0] po; reg [4:0] cnt;  @(posedge c or posedge notcs)  begin   if (notcs==1)   begin     cnt <= 4'b0000;   end   else if (cnt <= 5'd15)   begin     po[cnt] <= si;     cnt <= cnt + 1'b1;   end   else   begin     cnt <= cnt;   end end   endmodule   module spi(   input clock,   input notcs,   input  [15:0] po,   output reg led,   output reg sinusoidal,   output reg [11:0] dac_hi,   output reg [11:0] dac_lo,   output reg [5:0] blank_time,   output reg [5:0] blank_time_bcm );  @(posedge notcs) begin   led<=po[0]; end endmodule

after checking scope external device works correctly. when notcs high no data sent , clock off, when notcs low device starts clocking data in.
si serial input.
po parallel output.


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