design - Making state transitions using xilinx -

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i trying write asynchronous digital system fast clock. inputs determined 2 switches , button allow entering inputs.each input determines allows passing state. used internal clock b8 of digilent basys2 board. seem second state correctly can't other states. behavioral simulation gave expected results. here implementation,

entity states port ( x : in  std_logic;        y : in  std_logic;        clock : in  std_logic;        input : in  std_logic); end states;  architecture behavioral of state     signal ff : std_logic_vector (2 downto 0):="000"; begin process(clock) begin     if(rising_edge(clock))         if(input='1')             ff(0)<= (((ff(1)) , (ff(2)) , (not x) , y) or (ff(0)));             ff(1)<= (((not ff(0)) , (not ff(1)) , (ff(2)) , x , (not      y));             ff(2)<= (((not ff(0)) , (not ff(1)) , (not ff(2)) , x , y)                 or ((not ff(0)) , (ff(1)) , (not ff(2)) , (not x) , (not y)));             z <= (((not ff(0)) , (ff(1)) , (ff(2)) , (not x) , y) or (ff(0)));         end if;       end if; end process; end behavioral;

and here board assignments,

net "clock"  loc = "b8"  ; net "input"  loc = "c11"  ; net "x"  loc = "l3"  ; net "y"  loc = "p11"  ;

why simulation gave expected results tests on board didn't. appreciate help.

ok guys ve solved problem.the simulation worked board didnt because in simulation inputs given 1 time in rising edge.(i manipulate clock hand , create rising edge whenever want.)but in internal clock b8 clock changes fast takes input infinitely many times in seconds.to fix put clock g12 give clock hand (just in simulation)


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