C SPI latch pulse happening too soon -

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i'm trying interface 2 max7219 drivers using 9s12. problem when send data, latch pulse happening before spi transfer has been completed. http://imgur.com/bgd1sb9

attached picture shows pulse happening while spi clock , data still being sent in.

void max7219init(void)  {      int8u count =0;        setlow(portp, pin6);    /* need set low on startup */      (count = 1; count <= 2; count++){ //run twice send data 2 max7219          spimx(0x0f, 0xcd);       }      pulse(portp, pin6);        while (1) ;    }    void spimx(int8u address, int8u data)  {           while((spi0sr & sptef) == 0){} /*wait previous transmit */      spi0dr = (int8u)(address & 0b00001111);                /*initiate transfer */      while((spi0sr & spif) == 0){}  /*wait new data */           while((spi0sr & sptef) == 0){} /*wait previous transmit */      spi0dr = data;                /*initiate transfer */      while((spi0sr & spif) == 0){}  /*wait new data */     }

what causing pulse early? hope question makes sense. thanks

at moment send pulse, spi still transmitting data. must wait until spi has completed all pending transfers, not wait tranmit buffer being empty (i suppose spi double-buffered: tx buffer plus shift register, common).

so, either spi module has status bit signals "transmission complete" (on stm32 called "busy" reversed signalling on spi). or, if there no such flag, should use timer wait proper number of clocks elapsed. (start timer aftersending last word spi timeout value >= tranmit duration according spi clock , number of bits per transfer).

ok, had close , there no "complete/busy/idle flag. have wait each bytes trasnmitted using receive flag (see below)

void spimx(int8u address, int8u data) {     spi0dr = (int8u)(address & 0b00001111); // send address     while ( !(spi0sr & spif) ) ;            // wait until shifted     spi0dr;                                 // explaination below     spi0dr = data;                          // send data     while ( !(spi0sr & spif) ) ;            // wait until shifted     spi0dr;                                 // explaination below     // here spi idle }

due bidirectional nature of spi, if data has been received, stored byte has been transmitted. no actual need test sptef. @ beginning, no need spi has been empty last call (see below warning).

to clear spiif flag, have read data register. not need data drop (dummy read). otherwise, flag stay set forever , wait-loops terminate instantly. , result in behaviour shown.

note use no other funcrtion writing spi after initialization. otherwise has conform same procedure.


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