computer architecture - Tomasulo's algorithm + MIPS 5 stages pipeline + branch prediction -

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i'm learning tomasulo's algorithm , think understand it. can't figure out how integrated mips 5 stage pipeline discussed in hennessy , patterson? how 1 integrate branch prediction tomasulo? appreciated.

tomasulo's keeps track of dynamic scheduling of instructions comes in play when after decode have multiple ports execute different instructions hardware resources instructions wait, schedule, forward result. mips 5 stage in-order pipeline can not issue/dispatch multiple instructions in same cycle nor can go out of order in pipeline.

when see branch in front end of pipeline have make decision fetch next instruction, branch target or pc++. branch resolution takes time, , if wait, 3 or 20 cycles depending on processor, end inserting many bubbles. branch prediction (bp) start fetching somewhere confidence.

the link between bp , tomasulo's can bridged reorder buffer, register files capable of handling misprediction recovery. there many other things need start. know prediction made wrong, when calculate branch, clear rob , every possible buffer, pipeline stage, intermediate results affected instructions on speculated path until last committed instruction , restart fetching correct pc.

branch misprediction on latest processor costly , there tons of optimizations mitigate , make bps more accurate.

hope helps.


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